Magnetic memories are often used in storing data. One type of memory currently of interest utilizes magnetic tunneling junctions in the memory cells. A magnetic tunneling junction typically includes two ferromagnetic layers separated by a thin insulating layer. The insulating layer is thin enough to allow charge carriers to tunnel between the ferromagnetic layers. The resistance of the magnetic tunneling junction depends upon the orientation of the magnetic tunneling junctions.
FIGS. 1 and 2 depict a conventional memory array 1 using the conventional memory cell 2. The conventional array 1 is shown in FIG. 2 as including four conventional memory cells 2, labeled 2, 2′, 2″, and 2′″ in FIG. 2. Each conventional memory cell 2, 2′, 2″, and 2′″ includes a magnetic tunneling junction 10 and a transistor 40. The transistor 40 includes a drain 42, a source 46 and a gate 44. The memory cells 2, 2′, 2″, and 2′″ are coupled to bit lines 20 and 20′ and bit line selection 56 and to word line selection 54 via word lines 50 and 50′. The bit lines 20 and 20′ are coupled to the magnetic tunneling junctions 10, while the word lines 50 and 50′ are coupled to the gates 44 of the transistors 40. Also depicted are digit lines 30 and 30′ which carry current that applies a field to the appropriate conventional memory cells 2, 2′, 2″, and 2′″ during writing.
FIG. 3 depicts a conventional method 70 for writing to the memory cells 2, 2′, 2″, and 2′″. A bit line current, IB, is pulsed to the selected cell 2, 2′, 2″, or 2′″ through the bit line 20 or 20′ at the same time that a digit current, ID, is pulsed through the appropriate digit line 30 or 30′, via step 72. Thus, the write currents IB and ID are simultaneously provided to the selected cell in step 72. The direction of the digit current determines the orientation of the free layer in the magnetic tunneling junction 10 and, therefore, the state of the magnetic tunneling junction 10. For example, if the cell 2 is to be written, the write currents IB and ID are provided through the bit line 20 and the digit line 50, respectively. It is determined whether there are other cells 2, 2′, 2″, or 2′″ to program, via step 74. If not, then the method 70 terminates. If there are other cells 2, 2′, 2″, or 2′″ to program, then a new cell 2, 2′, 2″, or 2′″ is selected, via step 76. Step 72 is then repeated to program the new cell.
Although the conventional memory array 1 and the conventional memory cells 2, 2′, 2″, and 2′″ function, one of ordinary skill in the art will readily recognize that the power consumed using the conventional method 70 is relatively large. In particular, as described above, the bit line current and digit current are pulsed for each cell being programmed. Thus, assume that N cells are being programmed with a zero or a one, and the line voltages for the bit line 20 and 20′ and the digit line 30 or 30′ are VB and VD, respectively. Also assume that the currents ID and IB are pulsed for a time, τ. The energy required to switch N cells to the desired states is given by Nτ(IDVD+IBVB). Because this relatively large amount of energy is consumed when programming the conventional memory array 1, battery life of a product using the conventional memory 1 may be less than desired.
Accordingly, what is needed is a system and method for providing a magnetic memory having improved power consumption. The present invention addresses such a need.